RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2.1.1. LP-Serial Register Block Header

Table 88.  LP-Serial Register Block Header — 0x100
Field Bits Access Function Default
EF_PTR [31:16] RO Hard-wired pointer to the next block in the data structure. The value in this field is the address of the LP-Serial Lane Extended Features block, which is 0x200. 16'h0200
EF_ID [15:0] RO Hard-wired extended features ID. 16'h0200

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