RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.5.2. I/O Slave Address Mapping Registers

The registers define windows in the Avalon® -MM address space that are used to determine the outgoing request packet’s ftype, DESTINATION_ID, priority, and address fields. There are up to 16 register sets, one for each possible address mapping window. The 16 possible register address offsets are shown below the table titles.
Table 144.  Input/Output Slave Mapping Window n Base Offset: 0x10400, 0x10410, 0x10420, 0x10430, 0x10440, 0x10450, 0x10460, 0x10470, 0x10480, 0x10490, 0x104A0, 0x104B0, 0x104C0, 0x104D0, 0x104E0, 0x104F0
Field Bits Access Function Default
BASE [31:4] RW Start of the Avalon® -MM address window to be mapped. The four least significant bits of the 32-bit base are assumed to be all zeros. 28'h0
RSRV [3:0] RO Reserved. 4'h0
Table 145.  Input/Output Slave Mapping Window n MaskOffset: 0x10404, 0x10414, 0x10424, 0x10434, 0x10444, 0x10454, 0x10464, 0x10474, 0x10484, 0x10494, 0x104A4, 0x104B4, 0x104C4, 0x104D4, 0x104E4, 0x104F4
Field Bits Access Function Default
MASK [31:4] RW 28 most significant bits of the mask for the address mapping window. The four least significant bits of the 32-bit mask are assumed to be zeros. 28'h0
RSRV [3] RO Reserved. 1'b0
WEN [2] RW Window enable. Set to one to enable the corresponding window. 1'b0
RSRV [1:0] RO Reserved. 2'b00
Table 146.  Input/Output Slave Mapping Window n Offset Offset: 0x10408, 0x10418, 0x10428, 0x10438, 0x10448, 0x10458, 0x10468, 0x10478, 0x10488, 0x10498, 0x104A8, 0x104B8, 0x104C8, 0x104D8, 0x104E8, 0x104F8
Field Bits Access Function Default
OFFSET [31:4] RW Bits [31:3] of the starting offset into the RapidIO address space. The three least significant bits of the 34-bit offset are assumed to be zeros. 28'h0
RSRV [3:2] RO Reserved. 2'b00
XAMO [1:0] RW Extended Address: two most significant bits of the 34-bit offset. 2'b00
Table 147.  Input/Output Slave Mapping Window n Control Offset: 0x1040C, 0x1041C, 0x1042C, 0x1043C, 0x1044C, 0x1045C, 0x1046C, 0x1047C, 0x1048C, 0x1049C, 0x104AC, 0x104BC, 0x104CC, 0x104DC, 0x104EC, 0x104FC
Field Bits Access Function Default
LARGE_DESTINATION_ID (MSB) [31:24] RW/RO MSB of the Destination ID if the system supports 16-bit device ID.

Reserved if the system does not support 16-bit device ID.

8'h00
DESTINATION_ID [23:16] RW Destination ID. 8'h00
RSRV [15:8] RO Reserved. 8'h00
PRIORITY [7:6] RW Request packet’s priority. 2’b11 is not a valid value for the PRIORITY field. Any attempt to write 2’b11 to this field is overwritten with 2’b10. 2'b00
RSRV [5:3] RO Reserved. 3'b000
CRF [2] RW Critical Request Flow bit. 1'b0
SWRITE_ENABLE [1] RW SWRITE enable. Set to one to generate SWRITE request packets. 42 1'b0
NWRITE_R_ENABLE [0] RW NWRITE_R enable.42 1'b0
42 Bits 0 and 1 (NWRITE_R_ENABLE and SWRITE_ENABLE) are mutually exclusive. An attempt to write ones to both of these fields at the same time is ignored, and that part of the register keeps its previous value.

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