RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

1.1. Features

The RapidIO II IP core has the following features:

  • Compliant with RapidIO Interconnect Specification, Revision 2.2, June 2011, available from the RapidIO Trade Association website.
  • Supports 8-bit or 16-bit device IDs.
  • Supports incoming and outgoing multi-cast events.
  • Provides a 128-bit wide Avalon® Streaming ( Avalon® -ST) pass-through interface for fully integrated implementation of custom user logic.
  • Physical layer features:
    • 1x / 2x / 4x serial with integrated transceivers.
    • Fallback to 1x from 4x and 2x modes.
    • Fallback to 2x from 4x mode.
    • All five standard serial data rates supported: 1.25, 2.5, 3.125, 5.0, and 6.25 Gbaud (gigabaud).
    • Long control symbol.
    • IDLE2 idle sequence
      • Extraction and insertion of command and status (CS) field.
      • Support for software control of local and link-partner transmitter emphasis.
      • Insertion of clock compensation sequences.
    • Receive/transmit packet buffering, scrambling/descrambling, flow control, error detection and recovery, packet assembly, and packet delineation.
    • Automatic freeing of resources used by acknowledged packets.
    • Automatic retransmission of retried packets.
    • Scheduling of transmission, based on priority.
    • Software support for ackID synchronization.
    • Virtual channel (VC) 0 support.
    • Reliable traffic (RT) support.
    • Critical request flow (CRF) support.
  • Transport layer features:
    • Supports multiple Logical layer modules.
    • Supports an Avalon® -ST pass-through interface for custom implementation of capabilities such as data streaming and message passing.
    • A round-robin, priority-supporting outgoing scheduler chooses packets to transmit from various Logical layer modules.
  • Logical layer features:
    • Generation and management of transaction IDs.
    • Automatic response generation and processing.
    • Response Request Timeout checking.
    • Capability registers (CARs), command and status registers (CSRs), and Error Management Extensions registers.
    • Direct register access, either remotely or locally.
    • Maintenance master and slave Logical layer modules.
    • Input/Output Avalon® Memory-Mapped ( Avalon® -MM) master and slave Logical layer modules with 128-bit wide datapath and burst support.
    • Doorbell module supporting 16 outstanding DOORBELL packets with time-out mechanism.
    • Optional preservation of transaction order between outgoing DOORBELL messages and I/O write requests.
    • Registers and interrupt indicate NWRITE_R transaction completion.
    • Preservation of transaction order between outgoing I/O read requests and I/O write requests from Avalon® -MM interfaces.
  • Cycle-accurate simulation models for use in Intel® -supported VHDL and Verilog HDL simulators.
  • IEEE-encrypted HDL simulation models for improved simulation efficiency.
  • Support for Intel® FPGA IP Evaluation Mode.

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