RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

7.2.1. Reset, Initialization, and Configuration

The clocks that drive the testbench are defined and generated in the tb_rio.sv file. The frequencies used for each of the clocks depend on the configuration of the variation.

The reset sequence is simple — the main reset signal for the DUT and the sister_rio IP core, rst_n, is driven low at the beginning of the simulation, is kept low for 200 ns, and is then deasserted. The testbench also includes two Transceiver PHY Reset Controller IP cores, connected to the DUT and sister IP core. While rst_n is asserted, the reset input signal to the Transceiver PHY Reset Controller IP core is also asserted.

After rst_n is deasserted, the testbench waits until both the DUT and the sister_rio modules have driven their port_initialized output signals high. These signal transitions indicate that both IP cores have completed their initialization sequence. The testbench then waits an additional 5000 ns, to allow time for a potential reset link-request control symbol exchange between the DUT and the sister_rio module. The testbench again waits until both the DUT and the sister_rio modules have driven their port_initialized output signals high. Following the 5000 ns wait, the testbench checks that the port initialization process completed successfully by reading the Error and Status CSR to confirm the expected values of the PORT_OK and PORT_UNINIT register bits. These register fields indicate that the link is established and the Physical layer is ready to exchange traffic.

Next, basic programming of the internal registers is performed in the DUT and the sister_rio module.
Table 182.  Testbench Registers
Module Register Address Register Name Description Value
rio 0x00060 Base Device ID CSR Program the DUT to have an 8-bit base device ID of 0xAB or a 16-bit device ID of 0xABAB. 32'h00AB_FFFF or 32’h00FF_ABAB
rio 0x0013C General Control CSR Enable Request packet generation by the DUT. 32'h6000_0000
sister_rio 0x00060 Base Device ID CSR Program the sister_rio module to have an 8-bit base device ID of 0xCD or a 16-bit device ID of 0xCDCD. 32'h00CD_FFFF or 32’h00FF_CDCD
sister_rio 0x0013C General Control CSR Enable Request packet generation by the sister_rio module. 32'h6000_0000
rio 0x1040C Input/Output Slave Window 0 Control Set the DESTINATION_ID for outgoing transactions to a value 0xCD or 0xCDCD. The width of the DESTINATION_ID field depends on the sister_rio device ID width. This value matches the base device ID of the sister_rio module. 32'h00CD_0000 or 32'hCDCD_0000
rio 0x10404 Input/Output Slave Window 0 Mask Define the Input/Output Avalon-MM Slave Window 0 to cover the whole address space (mask set to all zeros) and enable it. 32'h0000_0004
rio 0x10504 Input/Output Slave Interrupt Enable Enable the I/O slave interrupts. 32'h0000_000F
sister_rio 0x10304 Input/Output Master Window 0 Mask Enable the sister_rio I/O Master Window 0, which allows the sister_rio to receive I/O transactions. 32'h0000_0004
rio 0x1010C TX Maintenance Window 0 Control Set the DESTINATION_ID for outgoing MAINTENANCE packets to 0xCD or 0xCDCD, depending on the sister_rio device ID width. This value matches the base device ID of the sister_rio module. Set the hop count to 0xFF. 32'h00CD_FF00 or 32'hCDCD_FF00
rio 0x10104 TX Maintenance Window 0 Mask Enable the TX Maintenance window 0. 32'h0000_0004
Read and write tasks that are defined in the BFM instance sys_mnt_master_bfm program the DUT’s registers. Read and write tasks defined in the BFM instance sister_sys_mnt_master_bfm program the sister_rio module’s registers. For the exact parameters passed to these tasks, refer to the file tb_rio.v. The tasks drive read and write transactions across the Register Access Avalon-MM slave interface.

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