RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents
Give Feedback Port-Write Transmission

To send a RapidIO MAINTENANCE port-write packet to a remote device, you must program the transmit port-write control and data registers. You access these registers using the Register Access Avalon-MM slave interface. You must program the values for the following header fields in the corresponding fields in the Tx Port Write Control register:
  • priority
  • wrsize
The RapidIO II IP core assigns the following values to the fields of the MAINTENANCE port-write packet:
  • Assigns ftype the value of 4'b1000
  • Assigns ttype the value of 4'b0100
  • Calculates the values for the wdptr and wrsize fields of the transmitted packet from the size of the payload to be sent, as defined by the size field of the Tx Port Write Control register
  • Assigns the value of 0 to the Reserved source_tid and config_offset fields
The IP core creates the packet’s payload from the contents of the Tx Port Write Buffer sequence of registers starting at register address 0x10210. This buffer can store a maximum of 64 bytes. The IP core starts the packet composition and transmission process after you set the PACKET_READY bit in the Tx Port Write Control register. The RapidIO II IP core composes the MAINTENANCE port-write packet and transmits it on the RapidIO link.