RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2.2.1. LP-Serial Lane Register Block Header

Table 99.  LP-Serial Lane Register Block Header — 0x200
Field Bits Access Function Default
EF_PTR [31:16] RO Hard-wired pointer to the next block in the data structure, if one exists. If this IP core variation instantiates the Error Management Extensions registers, the value in this field is the address of the Error Management Extended Features block, which is 0x300. If this IP core variation does not instantiate the Error Management Extensions registers, the value of this field is determined by the Extended features pointer parameter in the RapidIO II parameter editor.  
EF_ID [15:0] RO Hard-wired extended features ID. 16'h000D

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