RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.3.7.2. User Receiving MAINTENANCE Write Requests

Table 26.  Maintenance Interface Usage Example: Receiving MAINTENANCE Write Request
User Operation Device ID Width Payload Size
Receive MAINTENANCE write request 8-bit 32-bit
The RapidIO II IP core generates write transfers on the Maintenance Avalon-MM master interface in response to Type 8 MAINTENANCE Write request packets on the RapidIO link with the following properties:
  • ttype has the value of 4'b0001, indicating a MAINTENANCE Write request
  • config_offset has a value that indicates an address outside the range of the RapidIO II IP core internal register set
Figure 24. Write Transfers on the Maintenance Avalon-MM Master InterfaceIt shows the signal relationships when the RapidIO II IP core presents a sequence of four write transfers on the Maintenance Avalon-MM master interface.
In the first active clock cycle, the RapidIO II IP core indicates the start of a write transfer by asserting the usr_mnt_write signal. Simultaneously, the IP core presents the target address on the usr_mnt_address bus and the data on the usr_mnt_writedata bus.

In this example, user logic does not assert the usr_mnt_waitrequest signal. However, when user logic asserts the usr_mnt_waitrequest signal during a write transfer, the IP core maintains the address and data values on the buses until at least one clock cycle after user logic deasserts the usr_mnt_waitrequest signal. User logic can use the usr_mnt_waitrequest signal to throttle requests on this interface until it is ready to process them.

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