RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.6.5. Logical/Transport Layer Address Capture

Table 157.  Logical/Transport Layer Address Capture CSR — Offset: 0x314
Field Bits Access Function Default
ADDRESS [31:3] RW Least significant 29 bits of the RapidIO address associated with the error (for requests, for responses if available). In the case of a Maintenance response with Error status, the IP core sets this field to the 21-bit config_offset value from the original request. 29'h0
RSRV [2] RO Reserved. 1'b0
XAMSBS [1:0] RW Extended address bits of the address associated with the error (for requests, for responses if available). 2'b00

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