2.9. Instantiating Multiple RapidIO II IP Cores in V-series FPGA devices
If you want to instantiate multiple RapidIO II IP cores that target an Arria® V, Arria® V GZ, Cyclone® V, or Stratix® V device, a few additional steps are required. These steps are not relevant for variations that target any Intel® Arria® 10 or Intel® Stratix® 10 devices.
The Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V transceivers are configured with the Native PHY IP core. When your design contains multiple RapidIO II IP cores, the Intel® Quartus® Prime Fitter handles the merge of multiple Native PHY IP cores in the same transceiver block automatically, if they meet the merging requirements.
If you have different RapidIO II IP cores in different transceiver blocks on your device, you may choose to include multiple Transceiver Reconfiguration Controllers in your design. However, you must ensure that the Transceiver Reconfiguration Controllers that you add to your design have the correct number of interfaces to control dynamic reconfiguration of all your RapidIO II IP core transceivers. The correct total number of reconfiguration interfaces is the sum of the reconfiguration interfaces for each RapidIO II IP core; the number of reconfiguration interfaces for each RapidIO II IP core is the number of channels plus one. You must ensure that the reconfig_togxb and reconfig_fromgxb signals of an individual RapidIO II IP core connect to a single Transceiver Reconfiguration Controller.
For example, if your design includes one ×4 RapidIO II IP core and three ×1 RapidIO II IP cores, the Transceiver Reconfiguration Controllers in your design must include eleven dynamic reconfiguration interfaces: five for the ×4 RapidIO II IP core, and two for each of the ×1 RapidIO II IP cores. The dynamic reconfiguration interfaces connected to a single RapidIO II IP core must belong to the same Transceiver Reconfiguration Controller. In most cases, your design has only a single Transceiver Reconfiguration Controller, which has eleven dynamic reconfiguration interfaces. If you choose to use two Transceiver Reconfiguration Controllers, for example, to accommodate placement and timing constraints for your design, each of the RapidIO II IP cores must connect to a single Transceiver Reconfiguration Controller.
In the example, Transceiver Reconfiguration Controller 0 has seven reconfiguration interfaces, and Transceiver Reconfiguration Controller 1 has four reconfiguration interfaces. Each sub-block shown in a Transceiver Reconfiguration Controller block represents a single reconfiguration interface. The example shows only one possible configuration for this combination of RapidIO II IP cores; subject to the constraints described, you may choose a different configuration.
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