2.3. Generating IP Cores
- In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device. In the Intel® Quartus® Prime Standard Edition software, this step is not required.
- In the IP Catalog (Tools > IP Catalog), locate and double-click RapidIO II (IDLE2 up to 6.25 Gbaud) Intel FPGA IP to customize. The New IP Variation window appears.
- Specify a top-level name for your custom Intel® FPGA IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file with one of the following names:
- <your_ip> .ip (When you generate Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX variations in the Intel® Quartus® Prime Pro Edition software)
- <your_ip> .qsys (When you generate Intel® Arria® 10 variations in the Intel® Quartus® Prime Standard Edition software)
- Click Create/OK. The parameter editor appears.
- Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following:
- Optionally select preset parameter values. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
- Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The software generates a testbench for your IP core when you create a simulation model. The synthesis and simulation files generate according to your specifications.
If you click Generate > Generate Testbench System in the IP Parameter Editor, and then click Generate, the Intel® Quartus® Prime software generates a testbench framework. However, the resulting testbench is composed of BFM stubs and does not exercise the RapidIO II IP core in any meaningful way. In addition, the testbench Qsys system that is generated does not connect correctly. To generate the IP core testbench, click Generate HDL, select Verilog or VHDL simulation model type for Create simulation model, and click Generate.
- To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
- Click Finish. Click Yes if prompted to add files representing the IP variation to your project. Optionally turn on the option to Automatically add Intel® Quartus® Prime IP Files to all projects. Click Project > Add/Remove Files in Project to add IP files at any time.
Figure 4. Adding IP Files to ProjectNote:
For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the generated .qsys file must be added to your project to represent IP and Platform Designer systems. For devices released prior to Intel® Arria® 10 devices, the generated .qip and .sip files must be added to your project for IP and Platform Designer systems.
- After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.
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