Introduction to Intel® FPGA IP Cores

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ID 683102
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA IP Cores
1. Introduction to Intel® FPGA IP Cores x
1.1. IP Catalog and Parameter Editor 1.2. Installing and Licensing Intel® FPGA IP Cores 1.3. Best Practices for Intel® FPGA IP 1.4. IP General Settings 1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 1.7. Modifying an IP Variation 1.8. Upgrading IP Cores 1.9. Simulating Intel® FPGA IP Cores 1.10. Synthesizing IP Cores in Other EDA Tools 1.11. Support for the IEEE 1735 Encryption Standard 1.12. Introduction to Intel® FPGA IP Cores Archives 1.13. Introduction to Intel® FPGA IP Cores Revision History
1.1. IP Catalog and Parameter Editor x
1.1.1. The Parameter Editor
1.2. Installing and Licensing Intel® FPGA IP Cores x
1.2.1. Intel® FPGA IP Evaluation Mode 1.2.2. Checking the IP License Status 1.2.3. Intel FPGA IP Versioning 1.2.4. Adding IP to IP Catalog
1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
1.5.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 1.5.2. Scripting IP Core Generation
1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
1.6.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
1.8. Upgrading IP Cores x
1.8.1. Upgrading IP Cores at Command-Line 1.8.2. Migrating IP Cores to a Different Device 1.8.3. Troubleshooting IP or Platform Designer System Upgrade
1.9. Simulating Intel® FPGA IP Cores x
1.9.1. Supported Simulators 1.9.2. Supported Simulation Flows 1.9.3. Generating IP Simulation Files 1.9.4. Scripting IP Simulation 1.9.5. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
1.9.4. Scripting IP Simulation x
1.9.4.1. Generating a Combined Simulator Setup Script
1.9.4.1. Generating a Combined Simulator Setup Script x
1.9.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 1.9.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts 1.9.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 1.9.4.1.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 1.9.4.1.5. Sourcing Synopsys VCS* Simulator Setup Scripts 1.9.4.1.6. Sourcing Synopsys VCS* MX Simulator Setup Scripts
1.9.5. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
1.9.5.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.9.5.2. Generating IP Functional Simulation Models ( Intel® Quartus® Prime Standard Edition)
1.10. Synthesizing IP Cores in Other EDA Tools x
1.10.1. Instantiating IP Cores in HDL
1.10.1. Instantiating IP Cores in HDL x
1.10.1.1. Accessing HDL Code Templates
1.10.1.1. Accessing HDL Code Templates x
1.10.1.1.1. Example Top-Level Verilog HDL Module 1.10.1.1.2. Example Top-Level VHDL Module
1. Introduction to Intel® FPGA IP Cores

1.9.4.1. Generating a Combined Simulator Setup Script

You can run the Generate Simulator Setup Script for IP command to generate a combined simulator setup script.

You can then source this combined script from a top-level simulation script. Click Tools > Generate Simulator Setup Script for IP (or use of the ip-setup-simulation utility at the command-line) to generate or update the combined scripts, after any of the following occur:

  • IP core initial generation or regeneration with new parameters
  • Intel® Quartus® Prime software version upgrade
  • IP core version upgrade
ip-setup-simulation Utility
Utility Syntax
ip-setup-simulation generates a combined, version-independent simulation script for all Intel® FPGA IP cores in your project. The command also automates regeneration of the script after upgrading software or IP versions. Use the compile-to-work option to compile all simulation files into a single work library if your simulation environment requires. Use the --use-relative-paths option to use relative paths whenever possible. 
ip-setup-simulation
 --quartus-project=<my proj>
 --output-directory=<my_dir>
 --use-relative-paths
 --compile-to-work

--use-relative-paths and --compile-to-work are optional. For command-line help listing all options for these executables, type: <utility name> --help.

To generate a combined simulator setup script for all project IP cores for each simulator:3
  1. Click Tools > Generate Simulator Setup Script for IP (or run the ip-setup-simulation utility). Specify the Output Directory and library compilation options. Click OK to generate the file. By default, the files generate into the /<project directory>/<simulator>/ directory using relative paths.
    Note: For designs with F-tile IP, do not turn on the Use top-level entity names from Quartus project option.
    Figure 18. Generate Simulator Setup Script for IP Dialog Box


  2. To incorporate the generated simulator setup script into your top-level simulation script, refer to the template section in the generated simulator setup script as a guide to creating a top-level script:
    1. Copy the specified template sections from the simulator-specific generated scripts and paste them into a new top-level file.
    2. Remove the comments at the beginning of each line from the copied template sections.
    3. Specify the customizations you require to match your design simulation requirements, for example:
      • Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level file. The top-level entity of your simulation is often a testbench that instantiates your design. Then, your design instantiates IP cores or Platform Designer systems. Set the value of TOP_LEVEL_NAME to the top-level entity.
      • If necessary, set the QSYS_SIMDIR variable to point to the location of the generated IP simulation files.
      • Specify any other changes, such as using the grep command-line utility to search a transcript file for error signatures, or e-mail a report.
  3. Re-run Tools > Generate Simulator Setup Script for IP (or ip-setup-simulation) after regeneration of an IP variation.

Section Content
Sourcing Aldec ActiveHDL or Riviera Pro Simulator Setup Scripts
Sourcing Cadence Incisive Simulator Setup Scripts
Sourcing Cadence Xcelium Simulator Setup Scripts
Sourcing ModelSim or QuestaSim Simulator Setup Scripts
Sourcing Synopsys VCS Simulator Setup Scripts
Sourcing Synopsys VCS MX Simulator Setup Scripts

Related Information
3 If your design contains one or more F-tile IPs, you must first perform Start Analysis & Elaboration and then Support-Logic Generation before performing these steps.
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