1.1. IP Catalog and Parameter Editor 1.2. Installing and Licensing Intel® FPGA IP Cores 1.3. Best Practices for Intel® FPGA IP 1.4. IP General Settings 1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 1.7. Modifying an IP Variation 1.8. Upgrading IP Cores 1.9. Simulating Intel® FPGA IP Cores 1.10. Synthesizing IP Cores in Other EDA Tools 1.11. Support for the IEEE 1735 Encryption Standard 1.12. Introduction to Intel® FPGA IP Cores Archives 1.13. Introduction to Intel® FPGA IP Cores Revision History
220.127.116.11.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 18.104.22.168.2. Sourcing Cadence Incisive* Simulator Setup Scripts 22.214.171.124.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 126.96.36.199.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 188.8.131.52.5. Sourcing Synopsys VCS* Simulator Setup Scripts 184.108.40.206.6. Sourcing Synopsys VCS* MX Simulator Setup Scripts
1.8.2. Migrating IP Cores to a Different Device
Migrate an Intel® FPGA IP variation when you want to target a different (often newer) device. Most Intel® FPGA IP cores support automatic migration. Some IP cores require manual IP regeneration for migration. A few IP cores do not support device migration, requiring you to replace them in the project. The Upgrade IP Components dialog box identifies the migration support level for each IP core in the design.
- To display the IP cores that require migration, click Project > Upgrade IP Components. The Description field provides migration instructions and version differences.
- To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade option is turned on for the IP cores, and click Perform Automatic Upgrade. The Status and Version columns update when upgrade is complete.
- To migrate an IP core that does not support automatic upgrade, double-click the IP core name, and click OK. The parameter editor appears. If the parameter editor specifies a Currently selected device family, turn off Match project/default, and then select the new target device family.
- Click Generate HDL, and confirm the Synthesis and Simulation file options. Verilog HDL is the default output file format. If you specify VHDL as the output format, select VHDL to retain the original output format.
- Click Finish to complete migration of the IP core. Click OK if the software prompts you to overwrite IP core files. The Device Family column displays the new target device name when migration is complete.
- To ensure correctness, review the latest parameters in the parameter editor or generated HDL.
Note: IP migration may change ports, parameters, or functionality of the IP variation. These changes may require you to modify your design or to re-parameterize your IP variant. During migration, the IP variation's HDL generates into a library that is different from the original output location of the IP core. Update any assignments that reference outdated locations. If a symbol in a supporting Block Design File schematic represents your upgraded IP core, replace the symbol with the newly generated <my_ip> .bsf. Migration of some IP cores requires installed support for the original and migration device families.
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