Introduction to Intel® FPGA IP Cores

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ID 683102
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA IP Cores
1. Introduction to Intel® FPGA IP Cores x
1.1. IP Catalog and Parameter Editor 1.2. Installing and Licensing Intel® FPGA IP Cores 1.3. Best Practices for Intel® FPGA IP 1.4. IP General Settings 1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 1.7. Modifying an IP Variation 1.8. Upgrading IP Cores 1.9. Simulating Intel® FPGA IP Cores 1.10. Synthesizing IP Cores in Other EDA Tools 1.11. Support for the IEEE 1735 Encryption Standard 1.12. Introduction to Intel® FPGA IP Cores Archives 1.13. Introduction to Intel® FPGA IP Cores Revision History
1.1. IP Catalog and Parameter Editor x
1.1.1. The Parameter Editor
1.2. Installing and Licensing Intel® FPGA IP Cores x
1.2.1. Intel® FPGA IP Evaluation Mode 1.2.2. Checking the IP License Status 1.2.3. Intel FPGA IP Versioning 1.2.4. Adding IP to IP Catalog
1.5. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
1.5.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 1.5.2. Scripting IP Core Generation
1.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
1.6.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
1.8. Upgrading IP Cores x
1.8.1. Upgrading IP Cores at Command-Line 1.8.2. Migrating IP Cores to a Different Device 1.8.3. Troubleshooting IP or Platform Designer System Upgrade
1.9. Simulating Intel® FPGA IP Cores x
1.9.1. Supported Simulators 1.9.2. Supported Simulation Flows 1.9.3. Generating IP Simulation Files 1.9.4. Scripting IP Simulation 1.9.5. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
1.9.4. Scripting IP Simulation x
1.9.4.1. Generating a Combined Simulator Setup Script
1.9.4.1. Generating a Combined Simulator Setup Script x
1.9.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 1.9.4.1.2. Sourcing Cadence Incisive* Simulator Setup Scripts 1.9.4.1.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 1.9.4.1.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 1.9.4.1.5. Sourcing Synopsys VCS* Simulator Setup Scripts 1.9.4.1.6. Sourcing Synopsys VCS* MX Simulator Setup Scripts
1.9.5. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
1.9.5.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 1.9.5.2. Generating IP Functional Simulation Models ( Intel® Quartus® Prime Standard Edition)
1.10. Synthesizing IP Cores in Other EDA Tools x
1.10.1. Instantiating IP Cores in HDL
1.10.1. Instantiating IP Cores in HDL x
1.10.1.1. Accessing HDL Code Templates
1.10.1.1. Accessing HDL Code Templates x
1.10.1.1.1. Example Top-Level Verilog HDL Module 1.10.1.1.2. Example Top-Level VHDL Module
1. Introduction to Intel® FPGA IP Cores

1.9.4.1.6. Sourcing Synopsys VCS* MX Simulator Setup Scripts

Follow these steps to incorporate the generated Synopsys VCS* MX simulation scripts for use in top-level project simulation scripts.
  1. The generated simulation script contains these template lines. Cut and paste the lines preceding the “helper file” into a new executable file. For example, vcsmx.sh. 
    # # Start of template
# # If the copied and modified template file is "vcsmx_sim.sh", run
# # it as: ./vcsmx_sim.sh
# # 
# # Do the file copy, dev_com and com steps
# source vcsmx_setup.sh
# SKIP_ELAB=1
      
# SKIP_SIM=1
# 
# # Compile the top level module 
# vlogan +v2k
     +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv"
  
# # Do the elaboration and sim steps
# # Override the top-level name
# # Override the sim options, so the simulation runs
# # forever (until $finish()).
# source vcsmx_setup.sh
# SKIP_FILE_COPY=1
# SKIP_DEV_COM=1
# SKIP_COM=1
# TOP_LEVEL_NAME="'-top top'"
# USER_DEFINED_SIM_OPTIONS=""
# # End of template
  2. Delete the first two characters of each line (comment and space), as shown below: 
    # Start of template
# If the copied and modified template file is "vcsmx_sim.sh", run
# it as: ./vcsmx_sim.sh
# 
# Do the file copy, dev_com and com steps
source vcsmx_setup.sh
SKIP_ELAB=1
SKIP_SIM=1
  
# Compile the top level module
vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv"
   
# Do the elaboration and sim steps
# Override the top-level name
# Override the sim options, so the simulation runs
# forever (until $finish()).
source vcsmx_setup.sh
SKIP_FILE_COPY=1
SKIP_DEV_COM=1
SKIP_COM=1
TOP_LEVEL_NAME="'-top top'"
USER_DEFINED_SIM_OPTIONS=""
# End of template
  3. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example: 
    TOP_LEVEL_NAME=”'-top sim_top'”
  4. Make the appropriate changes to the compilation of your top-level file, for example: 
    vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../sim_top.sv"
  5. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  6. Run the resulting top-level script from the generated simulation directory by specifying the path to vcsmx_sim.sh.
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