Introduction to Intel® FPGA IP Cores

ID 683102
Date 4/03/2023
Document Table of Contents

1.9.3. Generating IP Simulation Files

The Intel® Quartus® Prime software optionally generates the functional simulation model, any testbench (or example design), and vendor-specific simulator setup scripts when you generate an IP core. To specify options for the generation of IP simulation files, follow these steps:
  1. To specify your supported simulator and options for design simulation file generation, click Assignment > Settings > EDA Tool Settings > Simulation.
  2. To specify your supported simulator and options for IP simulation file generation, click Assignments > Settings > IP Settings and specify the following:
    • To enable automatic generation of simulation models for all IP in the project when you generate IP during compilation, turn on the Generate IP simulation model when generating IP option under IP Simulation.
    • To specify one or more supported simulators for which to generate setup scripts, turn on one or more simulator option, or disable all simulator options to generate scripts for all simulators automatically.
  3. To generate the simulation files, click Processing > Start Compilation to compile the design. The simulation models and setup scripts for the Intel FPGA IP generate in the <your_project>/<ip name>/sim/<vendor> directory.
Figure 15. Project-Wide IP Generation Settings
You can optionally override these project-level IP Settings when you generate HDL for individual IP cores with the IP parameter editor. Prior to generation, you can specify a supported simulator, or specify no simulator to generate the setup scripts for all simulators in the parameter editor.
Figure 16. Simulation Options in Generation Dialog Box