Introduction to Intel® FPGA IP Cores

ID 683102
Date 4/03/2023
Document Table of Contents Accessing HDL Code Templates

The Intel® Quartus® Prime software includes code examples or templates for inferred RAMs, ROMs, shift registers, arithmetic functions, and DSP functions optimized for Intel FPGA devices. To access HDL code templates to define these IP cores in HDL:
  1. Open a file in the text editor.
  2. Click Edit > Insert template.
  3. In the Insert Template dialog box, click the + icon to expand either the Verilog HDL category or the VHDL category, depending on the HDL you prefer.
  4. Under Full Designs, expand the navigation tree to display the type of functions you want to infer.
  5. Select the function to display the code in the Preview pane and click Insert.