Introduction to Intel® FPGA IP Cores

ID 683102
Date 4/03/2023
Document Table of Contents Example Top-Level Verilog HDL Module

Verilog HDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.
module MF_top (a, b, sel, datab, clock, result);
	   input [31:0] a, b, datab;
	   input clock, sel;
	   output [31:0] result;
	   wire [31:0] wire_dataa;	
	   assign wire_dataa = (sel)? a : b;  
	   altfp_mult inst1 (.dataa(wire_dataa), .datab(datab), .clock(clock), .result(result));
		       inst1.pipeline = 11,
		       inst1.width_exp = 8,
		       inst1.width_man = 23,
		       inst1.exception_handling = "no";