RapidIO II Intel® FPGA IP User Guide

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ID 683444
Date 9/28/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the RapidIO II Intel® FPGA IP 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Signals 6. Software Interface 7. Testbench 8. RapidIO II IP Core User Guide Archives 9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide A. Initialization Sequence B. Differences Between RapidIO II IP Core and RapidIO IP Core
1. About the RapidIO II Intel® FPGA IP x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grades 1.6. Release Information
1.1. Features x
1.1.1. Supported Transactions
1.3. IP Core Verification x
1.3.1. Simulation Testing 1.3.2. Hardware Testing 1.3.3. Interoperability Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Intel® FPGA IP Evaluation Mode 2.32.4. Generating IP Cores2.32.4. Generating IP Cores 2.32.4. Generating IP Cores2.32.4. Generating IP Cores 2.5. RapidIO II IP Core Testbench Files 2.6. Simulating IP Cores 2.7. Integrating Your IP Core in Your Design 2.8. Compiling the Full Design and Programming the FPGA 2.9. Instantiating Multiple RapidIO II IP Cores in V-series FPGA devices
2.32.4. Generating IP Cores2.32.4. Generating IP Cores x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.32.4. Generating IP Cores2.32.4. Generating IP Cores x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.6. Simulating IP Cores x
2.6.1. Simulating the Testbench with the ModelSim Simulator 2.6.2. Simulating the Testbench with the VCS Simulator 2.6.3. Simulating the Testbench with the NCSim Simulator 2.6.4. Simulating the Testbench with the Xcelium Parallel Simulator
2.7. Integrating Your IP Core in Your Design x
2.7.1. Dynamic Transceiver Reconfiguration Controller 2.7.2. Transceiver PHY Reset Controller 2.7.3. Transceiver Settings 2.7.4. Adding Transceiver Analog Settings for Arria V GZ and Stratix V Variations 2.7.5. External Transceiver PLL
3. Parameter Settings x
3.1. Physical Layer Settings 3.2. Transport Layer Settings 3.3. Logical Layer Settings 3.4. Capability Registers Settings 3.5. Command and Status Registers Settings 3.6. Error Management Registers Settings
3.1. Physical Layer Settings x
3.1.1. Mode Selection 3.1.2. Data Settings 3.1.3. Transceiver Settings
3.2. Transport Layer Settings x
3.2.1. Enable 16-Bit Device ID Width 3.2.2. Enable Avalon® -ST Pass-Through Interface 3.2.3. Disable Destination ID Checking
3.3. Logical Layer Settings x
3.3.1. Maintenance Module Settings 3.3.2. Doorbell Module Settings 3.3.3. I/O Master Module Settings 3.3.4. I/O Slave Module Settings
3.4. Capability Registers Settings x
3.4.1. Device Identity CAR 3.4.2. Device Information CAR 3.4.3. Assembly Identity CAR 3.4.4. Assembly Information CAR 3.4.5. Processing Element Features CAR 3.4.6. Switch Port Information CAR 3.4.7. Switch Route Table Destination ID Limit CAR 3.4.8. Data Streaming Information CAR 3.4.9. Source Operations CAR 3.4.10. Destination Operations CAR
3.5. Command and Status Registers Settings x
3.5.1. Data Streaming Logical Layer Control CSR 3.5.2. Port General Control CSR 3.5.3. Port 0 Control CSR 3.5.4. Lane n Status 0 CSR 3.5.5. Extended Features Pointer CSR
4. Functional Description x
4.1. Interfaces 4.2. Clocking and Reset Structure 4.3. Logical Layer Interfaces 4.4. Transport Layer 4.5. Physical Layer 4.6. Error Detection and Management
4.1. Interfaces x
4.1.1. Avalon® -MM Master and Slave Interfaces 4.1.2. Avalon-ST Interface 4.1.3. RapidIO Interface
4.2. Clocking and Reset Structure x
4.2.1. Avalon System Clock 4.2.2. Reference Clock 4.2.3. Recovered Data Clock 4.2.4. Clock Rate Relationships in the RapidIO II IP Core 4.2.5. Clock Domains in Your Platform Designer System 4.2.6. Reset for RapidIO II IP Cores
4.3. Logical Layer Interfaces x
4.3.1. Register Access Interface 4.3.2. Input/Output Logical Layer Modules 4.3.3. Maintenance Module 4.3.4. Doorbell Module 4.3.5. Avalon-ST Pass-Through Interface
4.3.1. Register Access Interface x
4.3.1.1. Non-Doorbell Register Access Operations 4.3.1.2. Register Access Interface Signals
4.3.2. Input/Output Logical Layer Modules x
4.3.2.1. Input/Output Avalon-MM Master Module 4.3.2.2. Input/Output Avalon-MM Slave Module 4.3.2.3. Avalon® -MM Burstcount and Byteenable Encoding in RapidIO Packets 4.3.2.4. Input/Output Avalon® -MM Slave Module Timing Diagrams
4.3.2.1. Input/Output Avalon-MM Master Module x
4.3.2.1.1. Input/Output Avalon-MM Master Interface Signals 4.3.2.1.2. Defining the Input/Output Avalon-MM Master Address Mapping Windows 4.3.2.1.3. RapidIO Packet Data Word Pointer and Size Encoding in Avalon® -MM Transactions 4.3.2.1.4. Input/Output Avalon-MM Master Module Timing Diagrams
4.3.2.2. Input/Output Avalon-MM Slave Module x
4.3.2.2.1. Input/Output Avalon-MM Slave Interface Signals 4.3.2.2.2. Initiating Read and Write Transactions 4.3.2.2.3. Defining the Input/Output Avalon-MM Slave Address Mapping Windows 4.3.2.2.4. Input/Output Slave Translation Window Example
4.3.3. Maintenance Module x
4.3.3.1. Maintenance Interface Transactions 4.3.3.2. Maintenance Interface Signals 4.3.3.3. Initiating MAINTENANCE Read and Write Transactions 4.3.3.4. Defining the Maintenance Address Translation Windows 4.3.3.5. Responding to MAINTENANCE Read and Write Requests 4.3.3.6. Handling Port-Write Transactions 4.3.3.7. Maintenance Interface Transaction Examples 4.3.3.8. Maintenance Packet Error Handling
4.3.3.3. Initiating MAINTENANCE Read and Write Transactions x
4.3.3.3.1. IP Core Actions
4.3.3.5. Responding to MAINTENANCE Read and Write Requests x
4.3.3.5.1. IP Core Actions
4.3.3.6. Handling Port-Write Transactions x
4.3.3.6.1. IP Core Actions 4.3.3.6.2. Port-Write Transmission 4.3.3.6.3. Port-Write Reception
4.3.3.7. Maintenance Interface Transaction Examples x
4.3.3.7.1. User Sending MAINTENANCE Write Requests 4.3.3.7.2. User Receiving MAINTENANCE Write Requests 4.3.3.7.3. User Sending MAINTENANCE Read Requests and Receiving Responses 4.3.3.7.4. User Receiving MAINTENANCE Read Requests and Sending Responses
4.3.4. Doorbell Module x
4.3.4.1. Preserving Transaction Order 4.3.4.2. Doorbell Module Interface Signals 4.3.4.3. Generating a Doorbell Message 4.3.4.4. Response to a DOORBELL Request 4.3.4.5. Receiving a Doorbell Message
4.3.5. Avalon-ST Pass-Through Interface x
4.3.5.1. Transaction ID Ranges 4.3.5.2. Pass-Through Interface Signals 4.3.5.3. Pass-Through Interface Usage Examples
4.3.5.3. Pass-Through Interface Usage Examples x
4.3.5.3.1. User Sending Write Request 4.3.5.3.2. User Receiving Write Request 4.3.5.3.3. User Sending Read Request and Receiving Read Response 4.3.5.3.4. User Receiving Read Request and Sending Read Response 4.3.5.3.5. User Sending Streaming Write Request 4.3.5.3.6. User Receiving Streaming Write Request
4.4. Transport Layer x
4.4.1. Receiver 4.4.2. Transmitter
4.5. Physical Layer x
4.5.1. Low-level Interface Receiver 4.5.2. Low-Level Interface Transmitter
4.6. Error Detection and Management x
4.6.1. Physical Layer Error Management 4.6.2. Logical Layer Error Management 4.6.3. Avalon-ST Pass-Through Interface
4.6.1. Physical Layer Error Management x
4.6.1.1. Protocol Violations 4.6.1.2. Fatal Errors
4.6.2. Logical Layer Error Management x
4.6.2.1. Maintenance Avalon-MM Slave 4.6.2.2. Maintenance Avalon-MM Master 4.6.2.3. Port-Write Reception Module 4.6.2.4. Port-Write Transmission Module 4.6.2.5. Input/Output Avalon-MM Slave 4.6.2.6. Input/Output Avalon-MM Master
5. Signals x
5.1. Global Signals 5.2. Physical Layer Signals 5.3. Logical and Transport Layer Signals 5.4. Error Management Extension Signals
5.2. Physical Layer Signals x
5.2.1. Status Packet and Error Monitoring Signals 5.2.2. Low Latency Signals 5.2.3. Transceiver Signals 5.2.4. Register-Related Signals
5.2.2. Low Latency Signals x
5.2.2.1. Multicast Event Signals 5.2.2.2. Link-Request Reset-Device Signals
5.3. Logical and Transport Layer Signals x
5.3.1. Avalon-MM Interface Signals 5.3.2. Avalon® -ST Pass-Through Interface Signals 5.3.3. Data Streaming Support Signals 5.3.4. Transport Layer Packet and Error Monitoring Signal
5.3.1. Avalon-MM Interface Signals x
5.3.1.1. Register Access Interface Signals 5.3.1.2. Input/Output Avalon-MM Master Interface Signals 5.3.1.3. Input/Output Avalon-MM Slave Interface Signals 5.3.1.4. Maintenance Interface Signals 5.3.1.5. Doorbell Module Interface Signals
5.4. Error Management Extension Signals x
5.4.1. Error Reporting Signals
6. Software Interface x
6.1. Memory Map 6.2. Physical Layer Registers 6.3. Transport and Logical Layer Registers
6.1. Memory Map x
6.1.1. CAR Memory Map 6.1.2. CSR Memory Map 6.1.3. LP-Serial Extended Features Block Memory Map 6.1.4. LP-Serial Lane Extended Features Block Memory Map 6.1.5. Error Management Extensions Extended Features Block Memory Map 6.1.6. Maintenance Module Registers Memory Map 6.1.7. I/O Logical Layer Master Module Registers Memory Map 6.1.8. I/O Logical Layer Slave Module Registers Memory Map 6.1.9. Doorbell Module Registers Memory Map
6.2. Physical Layer Registers x
6.2.1. LP-Serial Extended Features Block Memory Map 6.2.2. LP-Serial Lane Extended Features Block Memory Map
6.2.1. LP-Serial Extended Features Block Memory Map x
6.2.1.1. LP-Serial Register Block Header 6.2.1.2. Port Link Time-out Control CSR 6.2.1.3. Port Response Time-out Control CSR 6.2.1.4. Port General Control CSR 6.2.1.5. Port 0 Link Maintenance Request CSR 6.2.1.6. Port 0 Link Maintenance Response CSR 6.2.1.7. Port 0 Local AckID CSR 6.2.1.8. Port 0 Control 2 CSR 6.2.1.9. Port 0 Error and Status CSR 6.2.1.10. Port 0 Control CSR
6.2.2. LP-Serial Lane Extended Features Block Memory Map x
6.2.2.1. LP-Serial Lane Register Block Header 6.2.2.2. LP-Serial Lane n Status 0 6.2.2.3. LP-Serial Lane n Status 1 6.2.2.4. LP-Serial Lane n Status 2 6.2.2.5. LP-Serial Lane n Status 3 6.2.2.6. LP-Serial Lane n Status 4
6.3. Transport and Logical Layer Registers x
6.3.1. Capability Registers (CARs) 6.3.2. Command and Status Registers (CSRs) 6.3.3. Maintenance Module Registers 6.3.4. I/O Logical Layer Master Module Registers 6.3.5. I/O Logical Layer Slave Module Registers 6.3.6. Error Management Registers 6.3.7. Doorbell Message Registers
6.3.1. Capability Registers (CARs) x
6.3.1.1. CAR Memory Map 6.3.1.2. Device Identity CAR 6.3.1.3. Device Information CAR 6.3.1.4. Assembly Identity CAR 6.3.1.5. Assembly Information CAR 6.3.1.6. Processing Element Features CAR 6.3.1.7. Switch Port Information CAR 6.3.1.8. Source Operations CAR 6.3.1.9. Destination Operations CAR 6.3.1.10. Switch Route Table Destination ID Limit CAR 6.3.1.11. Data Streaming Information CAR
6.3.2. Command and Status Registers (CSRs) x
6.3.2.1. CSR Memory Map 6.3.2.2. Data Streaming Logical Layer Control CSR 6.3.2.3. Processing Element Logical Layer Control CSR 6.3.2.4. Local Configuration Space Base Address 0 CSR 6.3.2.5. Local Configuration Space Base Address 1 CSR 6.3.2.6. Base Device ID CSR 6.3.2.7. Host Base Device ID Lock CSR 6.3.2.8. Component Tag CSR
6.3.3. Maintenance Module Registers x
6.3.3.1. Maintenance Module Registers Memory Map 6.3.3.2. Maintenance Interrupt Control Registers 6.3.3.3. Transmit Maintenance Registers 6.3.3.4. Transmit Port-Write Registers 6.3.3.5. Receive Port-Write Registers
6.3.4. I/O Logical Layer Master Module Registers x
6.3.4.1. I/O Logical Layer Master Module Registers Memory Map 6.3.4.2. I/O Master Address Mapping Registers 6.3.4.3. I/O Master Interrupts
6.3.5. I/O Logical Layer Slave Module Registers x
6.3.5.1. I/O Logical Layer Slave Module Registers Memory Map 6.3.5.2. I/O Slave Address Mapping Registers 6.3.5.3. I/O Slave Interrupts 6.3.5.4. I/O Slave Transactions and Requests
6.3.6. Error Management Registers x
6.3.6.1. Error Management Extensions Extended Features Block Memory Map 6.3.6.2. Error Management Extensions Block Header 6.3.6.3. Logical/Transport Layer Error Detect 6.3.6.4. Logical/Transport Layer Error Enable 6.3.6.5. Logical/Transport Layer Address Capture 6.3.6.6. Logical/Transport Layer Device ID Capture 6.3.6.7. Logical/Transport Layer Control Capture 6.3.6.8. Port-Write Target Device ID 6.3.6.9. Packet Time-to-Live 6.3.6.10. Port 0 Error Detect 6.3.6.11. Port 0 Error Rate Enable 6.3.6.12. Port 0 Attributes Capture 6.3.6.13. Port 0 Packet/Control Symbol Capture 0 6.3.6.14. Port 0 Packet Capture 1 6.3.6.15. Port 0 Packet Capture 2 6.3.6.16. Port 0 Packet Capture 3 6.3.6.17. Port 0 Error Rate 6.3.6.18. Port 0 Error Rate Threshold
6.3.7. Doorbell Message Registers x
6.3.7.1. Doorbell Module Registers Memory Map 6.3.7.2. Rx Doorbell 6.3.7.3. Tx Doorbell 6.3.7.4. Doorbell Interrupt
7. Testbench x
7.1. Testbench Overview 7.2. Testbench Sequence 7.3. Testbench Completion 7.4. Transceiver Level Connections in the Testbench
7.2. Testbench Sequence x
7.2.1. Reset, Initialization, and Configuration 7.2.2. Maintenance Write and Read Transactions 7.2.3. SWRITE Transactions 7.2.4. NREAD Transactions 7.2.5. NWRITE_R Transactions 7.2.6. NWRITE Transactions 7.2.7. Doorbell Transactions 7.2.8. Port-Write Transactions 7.2.9. Transactions Across the AVST Pass-Through Interface
Product Discontinuance Notification
1. About the RapidIO II Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. RapidIO II IP Core User Guide Archives
9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide
A. Initialization Sequence
B. Differences Between RapidIO II IP Core and RapidIO IP Core

5.2.3. Transceiver Signals

Table 59.  Transceiver SignalsThese signals are connected directly to the transceiver block. In some cases these signals must be shared by multiple transceiver blocks that are implemented in the same device.
Signal Direction Description
reconfig_to_xcvr Input Driven from an external dynamic reconfiguration block. Supports the selection of multiple transceiver channels for dynamic reconfiguration. Note that not using a dynamic reconfiguration block that enables offset cancellation results in a non-functional hardware design.

The width of this bus is (C + 1) × 70, where C is the number of channels: 1, 2, or 4. This width supports communication from the Reconfiguration Controller with C + 1 reconfiguration interfaces—one dedicated to each channel and another for the transceiver PLL—to the transceiver.

If you omit the Reconfiguration Controller from your simulation model, you must ensure all bits of this bus are tied to 0.

This bus is available only in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V IP core variations.
reconfig_from_xcvr Output Driven to an external dynamic reconfiguration block. The bus identifies the transceiver channel whose settings are being transmitted to the dynamic reconfiguration block. If no external dynamic reconfiguration block is used, then this output bus can be left unconnected.

The width of this bus is (C + 1) × 46, where C is the number of channels: 1, 2, or 4. This width supports communication from the transceiver to C + 1 reconfiguration interfaces in the Reconfiguration Controller, one interface dedicated to each channel and an additional interface for the transceiver PLL.

This bus is available only in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V IP core variations.
tx_cal_busy[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_cal_busy[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
pll_locked Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. This signal is available only in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V IP core variations.
pll_powerdown Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. This signal is available only in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V IP core variations.
rx_digitalreset[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_digitalreset_stat[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core while using Intel® Stratix® 10 devices, which implements the appropriate reset sequence for the device.
rx_analogreset[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_analogreset_stat[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core while using Intel® Stratix® 10 devices, which implements the appropriate reset sequence for the device.
rx_ready[n:0 Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
tx_digitalreset[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
tx_digitalreset_stat[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core while using Intel® Stratix® 10 devices, which implements the appropriate reset sequence for the device.
tx_analogreset[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
tx_analogreset_stat[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core while using Intel® Stratix® 10 devices, which implements the appropriate reset sequence for the device.
tx_ready[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_is_lockedtodata[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_is_lockedtoref[n:0] Output Indicates that the CDR is locked to tx_pll_refclk.
rx_syncstatus[n:0] Output Indicates that the word aligner is synchronized to incoming data.
rx_signaldetect[n:0] Output Indicates that the lane detects a sender at the other end of the link: the signal is above the programmed signal detection threshold value.
Table 60.   Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX Transceiver Dynamic Reconfiguration Avalon® -MM Interface SignalsEach of these individual interfaces is an Avalon® -MM interface you use to access the hard PCS registers for the corresponding transceiver channel on the Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX devices. These signals are available if you turn on Enable transceiver dynamic reconfiguration in the RapidIO II parameter editor.
Signal Direction Description
reconfig_clk_ch0 Input Dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 0.
reconfig_reset_ch0 Input Dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 0.
reconfig_waitrequest_ch0 Output Dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 0. The RapidIO II IP core uses this signal to stall the requestor on the interconnect.
reconfig_read_ch0 Input Dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 0.
reconfig_write_ch0 Input Dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 0.
reconfig_address_ch0[9:0] Input Dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 0. The address is a word address, not a byte address.
reconfig_writedata_ch0[31:0] Input Dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 0.
reconfig_readdata_ch0[31:0] Output Dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 0.
reconfig_clk_ch1 Input Dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_reset_ch1 Input Dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_waitrequest_ch1 Output Dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 1. The RapidIO II IP core uses this signal to stall the requestor on the interconnect. This signal is available only in 2x and 4x variations.
reconfig_read_ch1 Input Dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_write_ch1 Input Dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_address_ch1[9:0] Input Dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 1. The address is a word address, not a byte address. This signal is available only in 2x and 4x variations.
reconfig_writedata_ch1[31:0] Input Dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_readdata_ch1[31:0] Output Dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_clk_ch2 Input Dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_reset_ch2 Input Dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_waitrequest_ch2 Output Dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 2. The RapidIO II IP core uses this signal to stall the requestor on the interconnect. This signal is available only in 4x variations.
reconfig_read_ch2 Input Dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_write_ch2 Input Dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_address_ch2[9:0] Input Dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 2. The address is a word address, not a byte address. This signal is available only in 4x variations.
reconfig_writedata_ch2[31:0] Input Dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_readdata_ch2[31:0] Output Dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_clk_ch3 Input Dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_reset_ch3 Input Dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_waitrequest_ch3 Output Dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 3. The RapidIO II IP core uses this signal to stall the requestor on the interconnect. This signal is available only in 4x variations.
reconfig_read_ch3 Input Dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_write_ch3 Input Dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_address_ch3[9:0] Input Dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 3. The address is a word address, not a byte address. This signal is available only in 4x variations.
reconfig_writedata_ch3[31:0] Input Dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_readdata_ch3[31:0] Output Dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations
To control the transceivers, you must implement the following blocks in your design:
  • For Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V variations: Dynamic reconfiguration block.
    The dynamic reconfiguration block lets you reconfigure the following PMA settings:
    • Pre-emphasis
    • Equalization
    • Offset cancellation
    • VOD on a per channel basis
  • For all variations: Reset controller block.
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