Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook

ID 683461
Date 9/29/2022
Public
Document Table of Contents

5.6.6.6.1. IOPLL IP Core Signal Interface with LVDS SERDES IP Core

Table 66.  Signal Interface between IOPLL and LVDS SERDES IP cores This table lists the signal interface between the output ports of the IOPLL IP core and the input ports of the LVDS SERDES IP core transmitter and receiver.
From the IOPLL IP core To the LVDS SERDES IP core transmitter To the LVDS SERDES IP core receiver
lvds_clk[0] (serial clock output signal)
  • Configure this signal using outclk0 in the PLL.
  • Select Enable LVDS_CLK/LOADEN 0 or Enable LVDS_CLK/LOADEN 0 & 1 option for the Access to PLL LVDS_CLK/LOADEN output port setting. In most cases, select Enable LVDS_CLK/LOADEN 0.

The serial clock output can only drive ext_fclk on the LVDS SERDES IP core transmitter and receiver. This clock cannot drive the core logic.

ext_fclk (serial clock input to the transmitter)

ext_fclk (serial clock input to the receiver)

loaden[0] (load enable output)

  • Configure this signal using outclk1 in the PLL.
  • Select Enable LVDS_CLK/LOADEN 0 or Enable LVDS_CLK/LOADEN 0 & 1 option for the Access to PLL LVDS_CLK/LOADEN output port setting. In most cases, select Enable LVDS_CLK/LOADEN 0.

ext_loaden (load enable to the transmitter)

ext_loaden (load enable for the deserializer)

This signal is not required for LVDS receiver in soft-CDR mode.

outclk2 (parallel clock output)

ext_coreclock (parallel core clock)

ext_coreclock (parallel core clock)

locked

pll_areset (asynchronous PLL reset port)

phout[7:0]

  • This signal is required only for LVDS receiver in DPA or soft-CDR mode.
  • Configure this signal by turning on Specify VCO frequency in the PLL and specifying the VCO frequency value.
  • Turn on Enable access to PLL DPA output port.

ext_vcoph

This signal is required only for LVDS receiver in DPA or soft-CDR mode.

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