ID
683520
Date
9/20/2022
Public
Visible to Intel only — GUID: sam1412833541467
Ixiasoft
Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Visible to Intel only — GUID: sam1412833541467
Ixiasoft
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Updated for: |
---|
Intel® Quartus® Prime Design Suite 22.1 |
IP Version 20.0.1 |
The LVDS SERDES IP configures the serializer/deserializer (SERDES) and dynamic phase alignment (DPA) blocks. The IP also supports LVDS channel placements, legality checks, and LVDS channel-related rule checks.
The LVDS SERDES IP core is available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices only. If you are migrating designs from Stratix® V, Arria® V, or Cyclone® V devices, you must migrate the ALTLVDS_TX and ALTLVDS_RX IP cores.
Section Content
Release Information
LVDS SERDES Intel FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel FPGA IP Signals
LVDS SERDES Intel FPGA IP Parameter Settings
LVDS SERDES Intel FPGA IP Timing
LVDS SERDES Intel FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 GX Devices
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