LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683520
Date 9/20/2022
Document Table of Contents

Aligning Word Boundaries

After initializing the LVDS SERDES IP in DPA or non-DPA mode, perform these steps to align the word boundaries.
  1. Assert the rx_bitslip_reset port for at least one parallel clock cycle, and then deassert the rx_bitslip_reset port.
  2. Begin word alignment by applying pulses as required to the rx_bitslip_ctrl port.

After the word boundaries are established on each channel, the interface is ready for operation.