LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683520
Date 9/20/2022
Document Table of Contents


The deserializer consists of shift registers. The deserialization factor determines the depth of the shift registers. The deserializer converts a 1-bit serial data stream into a parallel data stream based on the deserialization factor.

The load_enable is a pulse signal with a frequency equivalent to the fast clock divided by the deserialization factor.

Figure 3.  LVDS x8 Deserializer Waveform

Table 5.  LVDS Deserializer Signals
Signal Description
rx_in LVDS input data stream to the LVDS SERDES IP core channel
fast_clock Clock for the receiver
load_enable Enable signal for deserialization
rx_out[7:0] Deserialized data