LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
ID
683520
Date
9/20/2022
Public
Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Simulation Design Example
The simulation design example uses your LVDS SERDES IP parameter settings to build the IP instance connected to a non-synthesizable simulation driver.
Using the design example, you can run a simulation using a single command, depending on the simulator that you use. The simulation demonstrates how you can use the LVDS SERDES IP.
Note: The non-synthesizable simulation driver works for the transmitter or receiver mode. However, to function in any receiver mode, the driver requires bit slip.
Figure 14. LVDS SERDES IP Simulation
Generating and Using the Design Example
To generate the simulation design example from the source files for a Verilog simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VERILOGTo generate the simulation design example from the source files for a VHDL simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VHDLThe TCL script creates a sim directory that contains subdirectories—one for each supported simulation tool. You can find the scripts for each simulation tool in the corresponding directories.