LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520
Date 9/20/2022
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Document Table of Contents x
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Initialization and Reset x
Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES Intel® FPGA IP Parameter Settings x
LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES Intel® FPGA IP Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES Intel® FPGA IP Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES Intel® FPGA IP Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES Intel® FPGA IP Design Examples x
LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES Intel® FPGA IP PLL Settings

Table 11.  PLL Settings Tab
Parameter Value Description
Use external PLL
  • On
  • Off

Turn on to use an external PLL:

  • The IP does not instantiate a local PLL.
  • The IP creates a series of clock connections with the "ext" prefix. Connect these ports to an externally generated PLL.
  • For details about how to configure the external PLL, refer to the Clock Resource Summary tab of the parameter editor.

This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration.

Note: You must turn on this option if you want to place combined LVDS transmitter and receiver interfaces in the same I/O bank.
Desired inclock frequency —

Specifies the inclock frequency in MHz.

Actual inclock frequency —

Displays the closest inclock frequency to the desired frequency that can source the interface.

FPGA/PLL speed grade —

Displays the FPGA/PLL speed grade, which determines the operation range of the PLL.
Enable pll_areset port
  • On
  • Off

Turn on to expose the pll_areset port. You can use the pll_areset signal to reset the entire LVDS interface.

This setting is enabled if if you turn on Use external PLL.

Core clock resource type —

Specifies onto which clock network the IP core exports an internally generated coreclock.

Note: This feature will be supported in a future version of the Intel® Quartus® Prime software. Currently, use QSF assignments to manually specify this parameter.
Related Information
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