LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683520
Date 9/20/2022
Document Table of Contents

LVDS SERDES Intel® FPGA IP General Settings

Table 10.  General Settings Tab
Parameter Value Description
Functional mode
  • TX
  • RX Non-DPA
  • RX Soft-CDR

Specifies the functional mode of the interface.

Number of channels
  • TX—1 to 72
  • RX Non-DPA—1 to 24
  • RX DPA-FIFO—1 to 24
  • RX Soft-CDR—1 to 12

Specifies the number of serial channels in the interface.

  • If you use a dedicated reference clock for the TX, RX non-DPA, or RX DPA-FIFO, you must use one of the channels for the refclk pin. Use a dedicated reference clock to reduce jitter.
  • If you use a transmitter output clock, you must use one of the channels for the tx_outclock pin.

For an LVDS RX design, place the refclk pin on the same I/O bank as the receiver.

For an LVDS TX design:

  • For an interface with less than 23 channels (standalone), each interface requires a refclk pin on the same I/O bank.
  • For an interface with more than 23 channels, channels 23 to 71 can share one refclk input.
Data rate 150.0 to 1600.0

Specifies the data rate (in Mbps) of a single serial channel. The value is dependent on the Functional mode parameter settings.

SERDES factor 3, 4, 5, 6, 7, 8, 9, and 10

Specifies the serialization rate or deserialization rate for the LVDS interface.

Use backwards-compatible port names
  • On
  • Off
Turn on to use legacy top-level names that are compatible with the ALTLVDS_TX and ALTLVDS_RX IPs.