I/O Timing Analysis
Receiver Timing Analysis in Soft-CDR and DPA-FIFO Modes
The DPA hardware dynamically captures the received data in soft-CDR and DPA-FIFO modes. For these modes, the Timing Analyzer does not perform static I/O timing analysis.
Receiver Timing Analysis in Non-DPA Mode
In non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path. If there is additional board channel-to-channel skew, consider the total receiver channel-to-channel skew (RCCS) instead of TCCS where .
set ::RCCS($<lvds_instance_name>) <RCCS value in nanoseconds>
For example, set ::RCCS($my_lvds_instance) 0.0.
Alternatively, you can specify the RCCS value in the RCCS (ps) box under the Non-DPA Settings section in the Receiver Settings tab of the LVDS SERDES parameter editor. The RCCS value you specify in the parameter editor overrides the RCCS value in the .sdc file.
Transmitter Timing Analysis
For LVDS transmitters, the Timing Analyzer provides the transmitter channel-to-channel skew (TCCS) value in the TCCS report (report_TCCS) in the Intel® Quartus® Prime compilation report, which shows TCCS values for serial output ports. You can also get the TCCS value from the device datasheet.
TCCS is the maximum skew observed across the channels of data and TX output clock—the difference between the fastest and slowest data output transitions, including the TCO variation and clock skew.
Did you find the information on this page useful?