Intel® Cyclone® 10 GX Device Datasheet

ID 683828
Date 2/14/2022
Public
Document Table of Contents

High-Speed I/O Specifications

Table 37.  High-Speed I/O Specifications for Intel® Cyclone® 10 GX Devices

When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.

For LVDS applications, you must use the PLLs in integer PLL mode.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

The Intel® Cyclone® 10 GX devices support the following output standards using true LVDS output buffer types on all I/O banks:
  • True RSDS output standard with data rates of up to 360 Mbps
  • True mini-LVDS output standard with data rates of up to 400 Mbps
Symbol Condition –E5, –I5 –E6, –I6 Unit
Min Typ Max Min Typ Max
fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor 
W = 1 to 40 57 10 700 10 625 MHz
fHSCLK_in (input clock frequency) Single Ended I/O Standards Clock boost factor 
W = 1 to 40 57 10 625 10 525 MHz
fHSCLK_OUT (output clock frequency) 700 58 625 58 MHz
Transmitter True Differential I/O Standards - fHSDR (data rate) 59 SERDES factor J = 4 to 10 60 61 62 62 1434 62 1250 Mbps
SERDES factor J = 3 60 61 62 62 1076 62 938 Mbps
SERDES factor J = 2, uses DDR registers 62 275 63 62 250 63 Mbps
SERDES factor J = 1, uses DDR registers 62 275 63 62 250 63 Mbps
tx Jitter - True Differential I/O Standards Total jitter for data rate, 600 Mbps – 1.6 Gbps 200 250 ps
Total jitter for data rate, < 600 Mbps 0.12 0.15 UI
tDUTY 64 TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 %
tRISE & & tFALL 61 65 True Differential I/O Standards 180 200 ps
TCCS 64 59 True Differential I/O Standards 150 150 ps
Receiver True Differential I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 to 10 60 61 62 150 1434 150 1250 Mbps
SERDES factor J = 3 60 61 62 150 1076 150 938 Mbps
fHSDR (data rate) (without DPA) 59 SERDES factor J = 3 to 10 62 66 62 66 Mbps
SERDES factor J = 2, uses DDR registers 62 63 62 63 Mbps
SERDES factor J = 1, uses DDR registers 62 63 62 63 Mbps
DPA (FIFO mode) DPA run length 10000 10000 UI
DPA (soft CDR mode) DPA run length SGMII/GbE protocol 5 5 UI
All other protocols 50 data transition per 208 UI 50 data transition per 208 UI
Soft CDR mode Soft-CDR ppm tolerance 300 300 ± ppm
Non DPA mode Sampling Window 300 300 ps
57 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
58 This is achieved by using the PHY clock network.
59 Requires package skew compensation with PCB trace length.
60 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
61 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
62 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
63 The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements.
64 Not applicable for DIVCLK = 1.
65 This applies to default pre-emphasis and VOD settings only.
66 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

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