Intel® Cyclone® 10 GX Device Datasheet

ID 683828
Date 2/14/2022
Public
Document Table of Contents

Minimum Configuration Time Estimation

Table 55.  Minimum Configuration Time Estimation for Intel® Cyclone® 10 GX DevicesThe estimated values are based on the uncompressed configuration bit stream sizes in the Configuration Bit Stream Sizes for Intel® Cyclone® 10 GX Devices table.
Variant Product Line Active Serial 85 Fast Passive Parallel 86
Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms)
Intel® Cyclone® 10 GX GX 085 4 100 229.32 32 100 28.67
GX 105 4 100 229.32 32 100 28.67
GX 150 4 100 229.32 32 100 28.67
GX 220 4 100 229.32 32 100 28.67
85 The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table.
86 Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.

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