Intel® Cyclone® 10 GX Device Datasheet

ID 683828
Date 2/14/2022
Public
Document Table of Contents

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 33.  Memory Block Performance Specifications for Intel® Cyclone® 10 GX Devices
Memory Mode Performance
–E5, –I5 –E6 –I6 Unit
MLAB Single port, all supported widths (×16/×32) 570 490 490 MHz
Simple dual-port, all supported widths (×16/×32) 570 490 490 MHz
Simple dual-port with the read-during-write option set to Old Data, all supported widths 400 330 330 MHz
ROM, all supported width (×16/×32) 570 490 490 MHz
M20K Block Single-port, all supported widths 625 530 510 MHz
Simple dual-port, all supported widths 625 530 510 MHz
Simple dual-port with the read-during-write option set to Old Data, all supported widths 470 410 410 MHz
Simple dual-port with ECC enabled, 512 × 32 410 360 360 MHz
Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32 520 470 470 MHz
True dual port, all supported widths 600 480 480 MHz
ROM, all supported widths 625 530 510 MHz

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