Intel® Cyclone® 10 GX Device Datasheet

ID 683828
Date 2/14/2022
Document Table of Contents

Memory Output Clock Jitter Specifications

Table 43.  Memory Output Clock Jitter Specifications for Intel® Cyclone® 10 GX Devices

The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance.

The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.

Protocol Parameter Symbol Data Rate (Mbps) Min Max Unit
DDR3 Clock period jitter tJIT(per) 1,866 –40 40 ps
Cycle-to-cycle period jitter tJIT(cc) 1,866 –40 40 ps
Duty cycle jitter tJIT(duty) 1,866 –40 40 ps

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