Intel® Cyclone® 10 GX Device Datasheet

ID 683828
Date 2/14/2022
Public
Document Table of Contents

PS Configuration Timing

Table 52.  PS Timing Parameters for Intel® Cyclone® 10 GX Devices
Symbol Parameter Minimum Maximum Unit
tCF2CD nCONFIG low to CONF_DONE low 1,440 ns
tCF2ST0 nCONFIG low to nSTATUS low 960 ns
tCFG nCONFIG low pulse width 2 μs
tSTATUS nSTATUS low pulse width 268 3,000 79 μs
tCF2ST1 nCONFIG high to nSTATUS high 3,000 80 μs
tCF2CK  81 nCONFIG high to first rising edge on DCLK 3,010 μs
tST2CK 81 nSTATUS high to first rising edge of DCLK 10 μs
tDSU DATA[] setup time before rising edge on DCLK 5.5 ns
tDH DATA[] hold time after rising edge on DCLK 0 ns
tCH DCLK high time 0.45 × 1/fMAX s
tCL DCLK low time 0.45 × 1/fMAX s
tCLK DCLK period 1/fMAX s
fMAX DCLK frequency 125 MHz
tCD2UM CONF_DONE high to user mode 82 175 830 μs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (600 × CLKUSR period)
79 This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
80 This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
81 If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
82 The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.

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