LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683520
Date 9/20/2022
Document Table of Contents

Timing Analysis when Using PLL Core Clocks

If you use PLL core clocks in your design, the LVDS SERDES IP generation does not create clock settings for the PLL input and output. You must ensure the PLL clock settings are correct.

Some of the SERDES constraints are derived from the PLL clocks. Therefore, the PLL core clock settings must be generated before the LVDS SERDES IP core clock settings. In you project's .qsf, ensure that the line for the IOPLL IP core's .qip appears before the line for the LVDS SERDES IP core's .qip.

Add the following line in your .sdc file to ensure all the PLL clocks are derived correctly.
derive_pll_clocks -create_base_clocks