LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

ID 683520
Date 9/20/2022
Document Table of Contents


The serializer consists of two sets of registers.

The first set of registers captures the parallel data from the core using the LVDS fast clock. The load_enable clock is provided alongside the LVDS fast clock, to enable these capture registers once in each coreclock period.

After the data is captured, it is loaded into a shift register that shifts the LSB towards the MSB at one bit per fast clock cycle. The MSB of the shift register feeds the LVDS output buffer. Therefore, higher order bits precede lower order bits in the output bitstream.

Figure 2.  LVDS x8 Serializer WaveformThis figure shows the waveform specific to serialization factor of eight.

Table 4.  LVDS Serializer Signals
Signal Description

Data for serialization

(Supported serialization factors: 3–10)

fast_clock Clock for the transmitter
load_enable Enable signal for serialization
lvdsout LVDS output data stream from the LVDS SERDES IP core channel