LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520
Date 9/20/2022
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Document Table of Contents x
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
LVDS SERDES IP Core Functional Description x
Serializer DPA FIFO Bitslip Deserializer
LVDS SERDES IP Initialization and Reset x
Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment
Word Boundaries Alignment x
Aligning Word Boundaries
LVDS SERDES Intel® FPGA IP Parameter Settings x
LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary
LVDS SERDES Intel® FPGA IP Receiver Settings x
Receiver Input Clock Parameters Setup
LVDS SERDES Intel® FPGA IP Transmitter Settings x
Setting the Transmitter Output Clock Parameters
LVDS SERDES Intel® FPGA IP Timing x
I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths
I/O Timing Analysis x
Obtaining RSKM Report Obtaining TCCS Report
LVDS SERDES Intel® FPGA IP Design Examples x
LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example
Additional LVDS SERDES IP Core References x
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores
LVDS Interface with External PLL Mode x
IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES Intel® FPGA IP Receiver Settings

The parameter options in the Receiver Settings tab are available if you select the RX Non-DPA, RX DPA-FIFO, or RX Soft-CDR functional mode in the General Settings tab.
Table 12.  Receiver Settings Tab—Bitslip Settings
Parameter Value Description
Enable bitslip mode
  • On
  • Off

Turn on to add a bit slip block to the receiver data path and expose the rx_bitslip_ctrl port (one input per channel).

Every assertion of the rx_bitslip_ctrl signal adds one bit of serial latency to the data path of the specified channel.

Enable rx_bitslip_reset port
  • On
  • Off

Turn on to expose the rx_bitslip_reset port (one input per channel) that you can use to reset the bit slip.

Enable rx_bitslip_max port
  • On
  • Off

Turn on to expose the rx_bitslip_max port (one output per channel).

When asserted, the next rising edge of rx_bitslip_ctrl resets the latency of the bit slip to zero.

Bitslip rollover value Deserialization factor

Specifies the maximum latency that the bit slip can inject.

When the bit slip reaches the specified value, it rolls over and the rx_bitslip_max signal asserts.

The rollover value is set automatically to the deserialization factor.

Table 13.  Receiver Settings Tab—DPA Settings
Parameter Value Description
Enable rx_dpa_reset port
  • On
  • Off

Turn on to expose the rx_dpa_reset port that you can use to reset the DPA logic of each channel independently.

(Formerly known as rx_reset.)

Enable rx_fifo_reset port
  • On
  • Off

Turn on to use your logic to drive the rx_fifo_reset port to reset the DPA-FIFO block.

Enable rx_dpa_hold port
  • On
  • Off

Turn on to expose the rx_dpa_hold input port (one input per channel).

If set high, the DPA logic in the corresponding channel does not switch sampling phases.

(Formerly known as rx_dpll_hold.)

Enable DPA loss of lock on one change
  • On
  • Off
  • On—the IP drives the rx_dpa_locked signal low when the DPA changes phase selection from the initially locked position. When the DPA changes the phase selection back to the initial locked position, the IP drives the rx_dpa_locked signal high.
  • Off—the IP drives the rx_dpa_locked signal low when the DPA moves two phases in the same direction away from the initial locked position. When the DPA changes the phase selection to be within one phase or same phase as the initial locked position, the IP drives the rx_dpa_locked signal high.

Deassertion of rx_dpa_locked does not indicate that the data is invalid. Instead, the deassertion indicates that the DPA has changed phase taps to track variations between the inclock and rx_in data.

Intel recommends that you use data checkers to verify data accuracy.

Enable DPA alignment only to rising edges of data
  • On
  • Off
  • On—DPA logic counts only the rising edges of the incoming serial data
  • Off—DPA logic counts the rising and falling edges
Note: Intel recommends that you use this port only for high jitter systems and turn it off for typical applications.
(Simulation only) Specify PPM drift on the recovered clock(s) — Specifies the amount of phase drift the LVDS SERDES IP simulation model adds to the recovered rx_divfwdclks.
Note: This feature will be supported in a future version of the Intel® Quartus® Prime software.
Table 14.  Receiver Settings Tab—Non-DPA Settings
Parameter Value Description
Desired receiver inclock phase shift (degrees) —

Specifies, in degrees of the LVDS fast clock, the ideal phase delay of inclock with respect to transitions in the incoming serial data.

For example, specifying 180° implies that the inclock is center aligned to the incoming data.

Actual receiver inclock phase shift (degrees)

Depends on the fast_clock and inclock frequencies. Refer to the related information.

Specifies the closest achievable receiver inclock phase shift to the desired receiver inclock phase shift.

RCCS (ps) —

Specifies the RSSC value in picoseconds.

Depending on the order the Intel® Quartus® Prime software reads the project .sdc files, this value may override any RCCS value you specify in the .sdc file.

To avoid uncertainty, Intel recommends that you specify the RCCS value in only one of the locations.


Section Content
Receiver Input Clock Parameters Setup

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