Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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15.5.1.7. Timing Registers

You must optimize the following registers for your flash device’s speed grade and clock frequency. The NAND flash controller operates correctly with the power‑on reset values. However, functioning with power‑on reset values is a non‑optimal mode that provides loose timing (large margins to the signals).

Set the following registers in the config group to optimize the NAND flash controller for the speed grade of the connected device and frequency of operation of the flash controller:

  • twhr2_and_we_2_re
  • tcwaw_and_addr_2_data
  • re_2_we
  • acc_clks
  • rdwr_en_lo_cnt
  • rdwr_en_hi_cnt
  • max_rd_delay
  • cs_setup_cnt
  • re_2_re