Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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Document Table of Contents

3.5.5. Level 2 Memory System

  • 1 MB L2 cache, shared among four processors
    • 16-way set associative cache structure
    • 64 bytes per line
  • Snoop Control Unit (SCU) that provides data coherency and ECC protection
  • Interfaces to system through a 128-bit AMBA* 4 ACE bus