Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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2.2.6.1. Stratix 10 HPS SDRAM L3 Interconnect

The SDRAM L3 interconnect connects the HPS to the hard memory controller (HMC) that is located in the FPGA portion of the device. The SDRAM L3 interconnect is composed of the SDRAM adapter and the SDRAM scheduler, which are secured by firewalls. It supports AMBA* AXI* QoS for the FPGA fabric interfaces.

The SDRAM L3 interconnect implements the following high-level features:

  • Support for double data rate 4 (DDR4) and DDR3 SDRAM devices
  • Software-configurable priority scheduling per port
  • 8-bit Single Error Correction, Double Error Detection (SECDED) ECC with write-back, and error counters
  • Fully-programmable timing parameter support for all JEDEC®‑specified timing parameters
  • All ports support memory protection and mutual-exclusive accesses
  • FPGA-to-SDRAM interface—a configurable interface from the FPGA to the SDRAM scheduler, consisting of three ports