Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

17.7.3. EMAC HPS Interface Initialization

To initialize the Ethernet controller to use the HPS interface, specific software steps must be followed including selecting the correct PHY interface through the System Manager.

In general, the Ethernet Controller must be in a reset state during static configuration and the clock must be active and valid before the Ethernet Controller is brought out of reset.

  1. After the HPS is released from cold or warm reset, reset the Ethernet Controller module by setting the appropriate emac* bit in the per0modrst register in the Reset Manager.
  2. Configure the EMAC Controller clock to 250 MHz by programming the appropriate registers in the Clock Manager.
  3. Bring the Ethernet PHY out of reset to allow PHY to generate RX clocks.
    There are no registers to verify, but you can create the following custom logic block to cross check:
    • If the RX clock is routed through FPGA IO—you can use Signal Tap to check, or create a simple counter block with the RX clock as clock source to check if it runs.
    • If the RX clock is routed as HPS IO—you need to explore if the kernel application code is able to source through RX clock to check its status.
  4. When all the clocks are valid, program the following clock settings:
    1. Program the phy_intf_sel field of the emac* register in the System Manager to 0x1 or 0x2 to select RGMII or RMII PHY interface.
    2. Disable the Ethernet Controller FPGA interface by clearing the emac_* bit in the fpgaintf_en_3 register of the System Manager.
  5. Configure all of the EMAC static settings if the user requires a different setting from the default value. These settings include the AxPROT[1:0] and AxCACHE signal values, which are programmed in the emac* register of the System Manager.
  6. Execute a register read back to confirm the clock and static configuration settings are valid.
  7. After confirming the settings are valid, software can clear the emac* bit in the per0modrst register of the Reset Manager to bring the EMAC out of reset.
When these steps are completed, general Ethernet controller and DMA software initialization and configuration can continue.