Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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5.4. System Memory Management Unit Functional Description

When a master issues a read or write transaction, the SMMU performs the following steps:
  1. Observes the security state of the transaction that originates the request.
  2. Maps the incoming transaction to one of the 32 contexts using the incoming stream ID.
  3. Caches frequently used address ranges using the TLB in that master's TBU.
  4. Performs a memory page table walk automatically on a TLB address lookup miss.
  5. Applies memory attributes and translates the incoming address. This step is explained in the following Translation Stages section.
  6. Applies required fault handling for every transaction.