Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.5.2. Other HPS Interfaces

  • TPIU trace—sends trace data created in the HPS-FPGA fabric.
  • FPGA System Trace Macrocell (STM)—an interface that allows the FPGA fabric to send hardware events to be stored in the HPS trace data.
  • FPGA cross–trigger—an interface that allows the CoreSight trigger system to send triggers to IP cores in the FPGA, and vice versa.
  • DMA peripheral interface—multiple peripheral–request channels.
  • Interrupts—allow soft IP cores to supply interrupts directly to the MPU interrupt controller.
  • MPU standby and events—signals that notify the FPGA fabric that the MPU is in standby mode and signals that wake-up Cortex–A53 processors from a wait for event (WFE) state.
  • HPS debug interface – an interface that allows the HPS debug control domain (debug APB) to extend into FPGA.