Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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4.5.4. Distributed Virtual Memory Controller

The distributed virtual memory controller (DVM) allows communication between the TCU of the SMMU and the TLB of the Cortex® -A53 MPCore™ .

DVM protocol broadcasts and synchronizes control packets for TLB invalidations, instruction cache invalidations, and similar requests.

The coherency interconnect has two primary functions related to DVM.
  • When the SMMU sends a DVM message, the message broadcasts to the Cortex® -A53 MPCore™ in the form of a snoop request. The TCU within the SMMU broadcasts snoops, gathers responses and replies to the Cortex® -A53 MPCore™ .
  • The coherency interconnect also performs DVM synchronization tasks, which include sending synchronization snoops, gathering completion requests from the TCU in the SMMU, and eventually signaling back that the request has completed.

As part of the SMMU, TBUs sit between the master peripherals and the L3 interconnect. The FPGA-to-HPS HPS interface also passes through a TBU before interfacing with the CCU.

Each TBU contains a micro translation look-aside buffer (TLB) that holds cached page table walk results from the translation control unit (TCU). For every virtual memory transaction that a master initiates, its TBU compares the virtual address against the translations stored in its buffer to see if a physical translation exists. If a translation does not exist, the TCU performs a page table walk. This SMMU integration allows the master peripheral's driver to pass virtual addresses directly to the master peripheral without having to perform virtual to physical address translations through the operating system.

For more information about distributed virtual memory support and the SMMU, refer to the System Memory Management Unit chapter.