Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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4.5.6. Cache Coherency Unit Interrupts

You can enable the CCU to trigger the interrupt_ccu in the GIC when certain CCU events occur. The CCU logically ORs interrupt conditions from several mask registers to create interrupt_ccu.
  • Bridge Interrupt Mask register (*am_intm*): Each bridge has a corresponding Bridge Interrupt Mask register that controls interrupt triggers for read and write channel events and capture counter overflows.
  • CCC Interrupt Mask register (agent_ccc0_ccc_interrupt_mask) at offset 0x30190: This register controls event counter overflow, single-bit ECC error and multiple bit ECC error interrupts.