Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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15.5.1.3. Device Operation Control

This section provides a list of registers that you need to program while choosing to use multi‑plane or cache operations on the device. If the device does not support multi‑plane operations or cache operations, then these registers can be left at their power‑on reset values with no impact on the functionality of the NAND flash controller. Even if the device supports these sequences, the software does not need to use them. Software can leave these registers at their power‑on reset values.

Program the following registers in the config group to achieve the best performance from a given device:

  • Set flag bit in the multiplane_operation register in the config group to 1 if the device supports multi‑plane operations to access the data on the flash device connected to the NAND flash controller. If the flash controller is set up for multi‑plane operations, the number of pages to be accessed is always a multiple of the number of planes in the device.
  • If the NAND flash controller is configured for multi‑plane operation, and if the device has support for multi‑plane read command sequence, set the multiplane_read_enable register in the config group.
  • If the device implements multiplane address restrictions, set the flag bit in the multiplane_addr_restrict register to 1.
  • Initialize the die_mask and first_block_of_next_plane registers as per device requirements.
  • If the device supports cache command sequences, enable the cache_write_enable and cache_read_enable registers in the config group.
  • Clear the flag bit of the copyback_disable register in the config group to 0 if the device does not support the copyback command sequences. The register defaults to enabled state.
  • The read_mode, write_mode and copyback_mode registers, in the config group, currently need not be written by software, because the NAND flash controller is capable of using the correct sequences based on a combination of some multi‑plane or cache‑related settings of the NAND flash controller and the manufacturer ID. If at some future time these settings change, program the registers to accommodate the change.