Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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17.6.3.1. Transmit Descriptor

The application software must program the control bits TDES0[31:18] during the transmit descriptor initialization. When the DMA updates the descriptor, it writes back all the control bits except the OWN bit (which it clears) and updates the status bits[7:0].

With the advance timestamp support, the snapshot of the timestamp to be taken can be enabled for a given frame by setting Bit 25 (TTSE) of TDES0. When the descriptor is closed (that is, when the OWN bit is cleared), the timestamp is written into TDES6 and TDES7 as indicated by the status Bit 17 (TTSS) of TDES0.

Note: Only enhanced descriptor formats (4 or 8 DWORDS) are supported.
Note: When the advanced timestamp feature is enabled, software should set Bit 7 of Register 0 (Bus Mode Register), so that the DMA operates with extended descriptor size. When this control bit is clear, the TDES4-TDES7 descriptor space is not valid.
Figure 83. Transmit Enhanced Descriptor Fields - Format


The DMA always reads or fetches four DWORDS of the descriptor from system memory to obtain the buffer and control information.

Figure 84. Transmit Descriptor Fetch (Read) Format


Table 170.  Transmit Descriptor Word 0 (TDES0)
Bit Description

31

OWN: Own Bit

When set, this bit indicates that the descriptor is owned by the DMA. When this bit is cleared, it indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame transmission or when the buffers allocated in the descriptor are read completely. The ownership bit of the frame’s first descriptor must be set after all subsequent descriptors belonging to the same frame have been set to avoid a possible race condition between fetching a descriptor and the driver setting an ownership bit.

30

IC: Interrupt on Completion

When set, this bit enables the Transmit Interrupt (Register 5[0]) to be set after the present frame has been transmitted.

29

LS: Last Segment

When set, this bit indicates that the buffer contains the last segment of the frame. When this bit is set, the TBS1 or TBS2 field in TDES1 should have a non-zero value.

28

FS: First Segment

When set, this bit indicates that the buffer contains the first segment of a frame.

27

DC: Disable CRC

When this bit is set, the MAC does not append a CRC to the end of the transmitted frame. This bit is valid only when the first segment (TDES0[28]) is set.

26

DP: Disable Pad

When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this bit is cleared, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This bit is valid only when the first segment (TDES0[28]) is set.

25

TTSE: Transmit Timestamp Enable

When set, this bit enables IEEE1588 hardware timestamping for the transmit frame referenced by the descriptor. This field is valid only when the First Segment control bit (TDES0[28]) is set.

24

Reserved

23:22

CIC: Checksum Insertion Control. These bits control the checksum calculation and insertion. The following list describes the bit encoding:

■ 0x0: Checksum insertion disabled.

■ 0x1: Only IP header checksum calculation and insertion are enabled.

■ 0x2: IP header checksum and payload checksum calculation and insertion are enabled, but pseudoheader checksum is not calculated in hardware.

■ 0x3: IP Header checksum and payload checksum calculation and insertion are enabled, and pseudoheader checksum is calculated in hardware.

This field is valid when the First Segment control bit (TDES0[28]) is set.

21 TER: Transmit End of Ring

When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a descriptor ring.

20

TCH: Second Address Chained

When set, this bit indicates that the second address in the descriptor is the Next descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care” value.

TDES0[21] takes precedence over TDES0[20].

19:18

Reserved

17

TTSS: Transmit Timestamp Status

This field is used as a status bit to indicate that a timestamp was captured for the described transmit frame. When this bit is set, TDES2 and TDES3 have a timestamp value captured for the transmit frame. This field is only valid when the descriptor’s Last Segment control bit (TDES0[29]) is set.

16

IHE: IP Header Error

When set, this bit indicates that the MAC transmitter detected an error in the IP datagram header. The transmitter checks the header length in the IPv4 packet against the number of header bytes received from the application and indicates an error status if there is a mismatch. For IPv6 frames, a header error is reported if the main header length is not 40 bytes. Furthermore, the Ethernet Length/Type field value for an IPv4 or IPv6 frame must match the IPheader version received with the packet. For IPv4 frames, an error status is also indicated if the Header Length field has a value less than 0x5.

This bit is valid only when the Tx Checksum Offload is enabled. If COE detects an IP header error, it still inserts an IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload.

15

ES: Error Summary

Indicates the logical OR of the following bits:

■ TDES0[14]: Jabber Timeout

■ TDES0[13]: Frame Flush

■ TDES0[11]: Loss of Carrier

■ TDES0[10]: No Carrier

■ TDES0[9]: Late Collision

■ TDES0[8]: Excessive Collision

■ TDES0[2]: Excessive Deferral

■ TDES0[1]: Underflow Error

■ TDES0[16]: IP Header Error

■ TDES0[12]: IP Payload Error

14

JT: Jabber Timeout

When set, this bit indicates the MAC transmitter has experienced a jabber time-out. This bit is only set when Bit 22 (Jabber Disable) of Register 0 (MAC Configuration Register) is not set.

13

FF: Frame Flushed

When set, this bit indicates that the DMA or MTL flushed the frame because of a software Flush command given by the CPU.

12

IPE: IP Payload Error

When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP IP datagram payload. The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual number of TCP, UDP, or ICMP packet bytes received from the application and issues an error status in case of a mismatch.

11

LC: Loss of Carrier

When set, this bit indicates that a loss of carrier occurred during frame transmission (that is, the gmii_crs_i signal was inactive for one or more transmit clock periods during frame transmission). This bit is valid only for the frames transmitted without collision when the MAC operates in the half-duplex mode.

10

NC: No Carrier

When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during transmission.

9

LC: Late Collision

When set, this bit indicates that frame transmission is aborted because of a collision occurring after the collision window (64 byte-times, including preamble, in MII mode and 512 byte-times, including preamble and carrier extension, in GMII mode). This bit is not valid if the Underflow Error bit is set.

8

EC: Excessive Collision

When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If Bit 9 (Disable Retry) in Register 0 (MAC Configuration Register) is set, this bit is set after the first collision, and the transmission of the frame is aborted.

7

VF: VLAN Frame

When set, this bit indicates that the transmitted frame is a VLAN-type frame.

6:3

CC: Collision Count (Status field)

These status bits indicate the number of collisions that occurred before the frame was transmitted. This count is not valid when the Excessive Collisions bit (TDES0[8]) is set. The EMAC updates this status field only in the half-duplex mode.

2

ED: Excessive Deferral

When set, this bit indicates that the transmission has ended because of excessive deferral of over 24,288 bit times (155,680 bits times in 1,000-Mbps mode or if Jumbo frame is enabled) if Bit 4 (Deferral Check) bit in Register 0 (MAC Configuration Register) is set.

1

UF: Underflow Error

When set, this bit indicates that the MAC aborted the frame because the data arrived late from the Host memory. Underflow Error indicates that the DMA encountered an empty transmit buffer while transmitting the frame. The transmission process enters the Suspended state and sets both Transmit Underflow (Register 5[5]) and Transmit Interrupt (Register 5[0]).

0

DB: Deferred Bit

When set, this bit indicates that the MAC defers before transmission because of the presence of carrier. This bit is valid only in the half-duplex mode.

Table 171.  Transmit Descriptor Word 1 (TDES1)
Bit Description
31:29 Reserved
28:16 TBS2: Transmit Buffer 2 Size

This field indicates the second data buffer size in bytes. This field is not valid if TDES0[20] is set.

15:13 Reserved
12:0 TBS1: Transmit Buffer 1 Size

This field indicates the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]).

Table 172.  Transmit Descriptor 2 (TDES2)
Bit Description
31:0 Buffer 1 Address Pointer

These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address alignment.

Table 173.  Transmit Descriptor 3 (TDES3)
Bit Description
31:0 Buffer 2 Address Pointer (Next Descriptor Address)

Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address Chained (TDES0[20]) bit is set, this address contains the pointer to the physical memory where the Next descriptor is present. The buffer address pointer must be aligned to the bus width only when TDES0[20] is set. (LSBs are ignored internally.)

Table 174.  Transmit Descriptor 6 (TDES6)
Bit Description
31:0 TTSL: Transmit Frame Timestamp Low

This field is updated by DMA with the least significant 32 bits of the timestamp captured for the corresponding transmit frame. This field has the timestamp only if the Last Segment bit (LS) in the descriptor is set and Timestamp status (TTSS) bit is set.

Table 175.  Transmit Descriptor 7 (TDES7)
Bit Description
31:0 TTSH: Transmit Frame Timestamp High

This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame. This field has the timestamp only if the Last Segment bit (LS) in the descriptor is set and Timestamp status (TTSS) bit is set.