Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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25.4.7. Trace Port Interface Unit

The TPIU is a bridge between on-chip trace sources and an off-chip trace port. The TPIU receives trace data from the ATB bus slave and drives the trace data to a trace port analyzer.

The trace output is routed to a 32-bit interface to the FPGA fabric. The trace data sent to the FPGA fabric can be transported off-chip using available serializer/deserializer (SERDES) resources in the FPGA.
Table 216.  Trace Pins
Signal Description
h2f_tpiu_clk

TPIU trace clock output. TPIU generates this clock by dividing cs_atclk by 2.

Supported frequency: 200/100/50/25/12.5 MHz

h2f_tpiu_data[15:0]

16 least significant bits of trace data output of TPIU.

Data on this bus is synchronous to h2f_tpiu_clk and changes on both rising and falling edge of this clock.

Supported data rate: 400/200/100/50/25 Mb/sec

For more information, refer to the CoreSight Components Technical Reference Manual on the ARM® Infocenter website.