Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

18.6.1. Enabling SPRAM ECCs

The L3 interconnect has access to the SPRAM and is accessible through the USB OTG L3 slave interface. Software accesses the SPRAM through the directfifo memory space, in the USB OTG controller address space.

Note: Software cannot access the SPRAM beyond the 32‑KB range. Out-of-range read transactions return indeterminate data. Out-of-range write transactions are ignored.