Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.5.1.3. HPS-to-FPGA Clock Domain

The HPS-to-FPGA domain is used purely by the HPS-to-FPGA bridge. The FPGA drives the HPS-to-FPGA clock, which is asynchronous to all other clocks.

Table 66.  Clocks in the HPS-to-FPGA Domain
Group Clock Enables Nominal Ratio Reset Usage
soc2fpga_clk soc2fgpa_bridge_rst_n