Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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25.4.5.2.1. Distributed Virtual Memory Support

The system memory management unit (SMMU) in the HPS supports distributed virtual memory transactions initiated by masters.

As part of the SMMU, a translation buffer unit (TBU) sits between the ETR and the L3 interconnect. The ETR shares a TBU with the USB, NAND, and SD/MMC. An intermediate interconnect arbitrates accesses among the multiple masters before they are sent to the TBU. The TBU contains a micro translation lookaside buffer (TLB) that holds cached page table walk results from a translation control unit (TCU) in the SMMU. For every virtual memory transaction that this master initiates, the TBU compares the virtual address against the translations stored in its buffer to see if a physical translation exists. If a translation does not exist, the TCU performs a page table walk. This SMMU integration allows the ETR driver to pass virtual addresses directly to the ETR without having to perform virtual to physical address translations through the operating system.

For more information about distributed virtual memory support and the SMMU, refer to the System Memory Management Unit chapter.