Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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14.3.3. Intel Stratix 10 I/O Control Registers

The HPS provides control registers that allow the system to initialize the following I/O parameters at system startup:

  • Pin assignment for external oscillator clock input
  • Pin assignment for each HPS peripheral
  • HPS peripheral interfaces optionally exposed to FPGA logic
  • I/O cell configuration
Note: Software can only access the HPS I/O control registers in secure mode.

Control registers can be divided into the following groups:

  • Dedicated pin MUX registers
  • Dedicated configuration registers
  • FPGA access MUX registers
  • HPS oscillator clock input register
  • HPS JTAG pin MUX register

You program the control registers when you instantiate the HPS component at the time of system generation. When you configure the HPS component, Platform Designer determines the correct register settings, and places them in the boot loader code.