Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

17.7.4. DMA Initialization

This section provides the instructions for initializing the DMA registers in the proper sequence. This initialization sequence can be done after the EMAC interface initialization has been completed. Perform the following steps to initialize the DMA:

  1. Provide a software reset to reset all of the EMAC internal registers and logic. (DMA Register 0 (Bus Mode Register) – bit 0). 
  2. Wait for the completion of the reset process (poll bit 0 of the DMA Register 0 (Bus Mode Register), which is only cleared after the reset operation is completed). 
  3. Poll the bits of Register 11 (AXI Status) to confirm that all previously initiated (before software reset) or ongoing transactions are complete.
    Note: If the application cannot poll the register after soft reset (because of performance reasons), then it is recommended that you continue with the next steps and check this register again (as mentioned in step 12) before triggering the DMA operations.
  4. Program the following fields to initialize the Bus Mode Register by setting values in DMA Register 0 (Bus Mode Register):
    • Mixed Burst and AAL
    • Fixed burst or undefined burst
    • Burst length values and burst mode values
    • Descriptor Length (only valid if Ring Mode is used)
  5. Program the interface options in Register 10 (AXI Bus Mode Register). If fixed burst-length is enabled, then select the maximum burst-length possible on the bus (bits[7:1]).
  6. Create a proper descriptor chain for transmit and receive. In addition, ensure that the receive descriptors are owned by DMA (bit 31 of descriptor should be set). When OSF mode is used, at least two descriptors are required.
  7. Make sure that your software creates three or more different transmit or receive descriptors in the chain before reusing any of the descriptors.
  8. Initialize receive and transmit descriptor list address with the base address of the transmit and receive descriptor (Register 3 (Receive Descriptor List Address Register) and Register 4 (Transmit Descriptor List Address Register) respectively).
  9. Program the following fields to initialize the mode of operation in Register 6 (Operation Mode Register):
    • Receive and Transmit Store And Forward
    • Receive and Transmit Threshold Control (RTC and TTC)
    • Hardware Flow Control enable
    • Flow Control Activation and De‑activation thresholds for MTL Receive and Transmit FIFO buffers (RFA and RFD)
    • Error frame and undersized good frame forwarding enable
    • OSF Mode
  10. Clear the interrupt requests, by writing to those bits of the status register (interrupt bits only) that are set. For example, by writing 1 into bit 16, the normal interrupt summary clears this bit (DMA Register 5 (Status Register)).
  11. Enable the interrupts by programming Register 7 (Interrupt Enable Register).
    Note: Perform step 12 only if you did not perform step 3.
  12. Read Register 11 (AHB or AXI Status) to confirm that all previous transactions are complete.
    Note: If any previous transaction is still in progress when you read the Register 11 (AXI Status), then it is strongly recommended to check the slave components addressed by the master interface.
  13. Start the receive and transmit DMA by setting SR (bit 1) and ST (bit 13) of the control register (DMA Register 6 (Operation Mode Register).