Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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15.4.5.1. Clock Generation

The clock manager sends the top level clock from the HPS.

The clock manager sends the 200 MHz clock, l4_mp_clk, to the NAND Flash Controller. This clock becomes the NAND reference clock called nand_mp_clk. The nand_mp_clk is divided by four and is used for input and output. Since the NAND places a 200 MHz limit on the clock, each of these generated clocks are 50 MHz and called nand_clk.